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revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary document title 128kx8 super low power and low voltage full cmos sram data sheets for 48-csp revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any questions, please contact the samsung branch office near your office, call or contact headquarters. rev . no. rev. 0.0 rev. 0.1 remark preliminary preliminary history - 1 st edition - package dimension finalized - 2 nd edition - change speed marking method marking was indicate speed at high power, that change to speed at low power draft data feb. 6 th, 1997 apr. 18 th, 1997
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary 128kx8 bit super low power and low voltage full cmos sram with 48-csp(chip scale package) the KM68FS1000Z and km68fr1000z family are fabricated by samsung s advanced full cmos process technology. the family can support various operating temperature ranges and has very small size with 0.75 ball pitch and 6 x 8 ball array. the family also support low data retention voltage for battery back- up operation with low data retention current. general description features summary ? process technology : 0.4 m m full cmos ? organization : 128kx8 ? power supply voltage KM68FS1000Z family : 2.3v(min) ~ 3.3v(max) km68fr1000z family : 1.8v(min) ~ 2.7v(max) ? low data retention voltage : 1.5v(min) ? three state output and ttl compatible ? package type : 48-csp with 0.75mm ball pitch name function name function a 0 ~a 16 address inputs vcc power we write enable input vss ground cs 1 ,cs 2 chip select input i/o 1 ~i/o 8 data inputs/outputs oe output enable n.c. no connection product family product family operating temp.range vcc range speed (ns) power dissipation pkg type standby (i sb1 ) operating (i cc2 ) KM68FS1000Z commercial (0~70 c) 2.3~3.3v 100*@v cc =3.0 0.3v 150*@v cc =2.5 0.2v 10 m a (max) 55ma(max) 30ma(max) 48-csp (6x8 ball area with 0.75mm ball pitch) km68fr1000z 1.8~2.7v 300*@v cc =2.0 0.2v 15ma(max) KM68FS1000Zi industrial (-40~85 c) 2.3~3.3v 100*@v cc =3.0 0.3v 150*@v cc =2.5 0.2v 10 m a (max) 55ma(max) 30ma(max) km68fr1000zi 1.8~2.7v 300*@v cc =2.0 0.2v 15ma(max) * see last page for package dimension. a 0 a 1 cs 2 a 3 a 6 a 8 i/o 5 a 2 we a 4 a 7 i/o 1 i/o 6 nc a 5 i/o 2 v ss v cc v cc v ss i/o 7 nc nc i/o 3 i/o 8 oe cs 1 a 16 a 15 i/o 4 a 9 a 10 a 11 a 12 a 13 a 14 48-csp pin top view functional block diagram a d d b u f f e r cell array a 0 ~a 16 i/o 1 ~ 8 cs 1 d e c o r d e r ctrl b u f f e r oe we cs 2 d . p a t h 1 2 3 4 5 6 a b c d e f g h samsung electronics co., ltd. reserves the right to change products and specifications without notice.
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary product list & ordering information product list * the meaning of 2.5v/3.0v, 150/100ns is that the operating v cc is ranged from 2.3v(min) to 3.3v(max) with speed 150ns @2.5v 0.2 and 100 ns @3.0v 0.3. this type of meaning is applied to other notations like the example. ** but in case of km68fr1000z-30, there is only one speed bin, 300ns though it supports wide range operating v cc. commercial temp product (0~70 c) industrial temp product (-40~85 c) part name function part name function KM68FS1000Z-15 km68fr1000z-30 48-csp, 2.5v/3.0v, 150/100ns 48-csp, 1.8v/2.5v, 300ns KM68FS1000Z-15 km68fr1000z-30 48-csp, 2.5v/3.0v, 150/100ns 48-csp, 1.8v/2.5v, 300ns ordering information km6 8 x x 1000 x x x - x x blank : low low power access time : 7=70ns, 8=85ns, 10=100ns, 12=120ns, operating temperature : blank=commercial, e=extended, i=industrial package type : g=sop, t=tsop forward, r=tsop reverse die version : blank=1 st generation density : 1000=1mbit process technology : f-full cmos(6-tr cell) organization : 8= x8 sec standard sram z=48-csp with 0.75mm pitch 15=150ns, 30=300ns s=2.3~3.3v, r=1.8~2.7v
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary absolute maximum ratings * * stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional opera tion should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.2 to 3.6v v - voltage on vcc supply relative to vss v cc -0.2 to 4.0v v - power dissipation p d 1.0 w - storage temperature t stg -55 to 150 c - operating temperature t a 0 to 70 c KM68FS1000Z km68fr1000z -40 to 85 c KM68FS1000Zi km68fr1000zi soldering temperature and time t solder 260 c, 5sec(lead only) - - recommended dc operating conditions * * 1) commercial product : t a =0 to 70 c, unless otherwise specified 2) industrial product : t a =-40 to 85 c, unless otherwise specified ** t a =25 c *** v il (min)=-1.5v for 30ns pulse width item symbol product min typ** max unit supply voltage vcc KM68FS1000Z family 2.3 2.5/3.0 3.3 v km68fr1000z family 1.8 2.0/2.5 2.7 v ground vss all family 0 0 0 v input high voltage v ih KM68FS1000Z family vcc=3.0 ?? 0.2v 2.2 - vcc+0.2 v vcc=2.5 ?? 0.2v 2.0 - vcc+0.2 v km68fr1000z family vcc=2.5 ?? 0.2v 2.0 - vcc+0.2 v vcc=2.0 ?? 0.2v 1.6 - vcc+0.2 v input low voltage v il all family -0.2*** - 0.4 v capacitance* (f=1mhz, t a =25 c) * capacitance is sampled not, 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary dc and operating characteristics 1) - commercial product t a =0 to 70 c, vcc=2.3v(min) ~ 3.3v(max) for 68fs1000z family, vcc=1.8v(min) ~ 2.7v(max)v for 68fr1000z family - industrial product t a =-40 to 85 c, vcc=2.3v(min) ~ 3.3v(max) for 68fs1000zi family, vcc=1.8v(min)~2.7v(max) for 68fr1000zi family. 2) the value has difference by 1 m a . measured at vcc=3.3v(max) 3) the value is not 100% tested but obtained statistically at temp=25 c 4) - the value is measured at vcc=3.0v 0.3v - i cc2 =30ma with 120ns cycle at vcc=2.5v 0.2v, but this value is not 100% tested but obtained statistically. - i cc2 =15ma with 300ns cycle at vcc=2.0v 0.2v, but this value is not 100% tested but obtained statistically. 5) the value is measured at vcc=3.0v 0.3v item symbol test conditions 1) min typ** max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or we =v il , v io =vss to vcc -1 - 1 m a operating power supply current i cc cs 1 =v il, cs 2 =v ih v in =v ih or v il , i io =0ma read - - 5 5) ma write - - 15 5) average operating current i cc1 cycle time=1 ? 100% duty, cs 1 0.2v, cs 2 3 v in 3 v cc -0.2v read - - 5 5) ma write - - 15 5) i cc2 min cycle, 100% duty, i io =0ma, cs 1 =v il, or cs 2 =v ih vcc=3.3v@100ns - - 55 4) ma vcc=2.7v@150ns - - 30 vcc=2.2v@300ns - - 15 output low voltage v ol i ol vcc=3.0v 2.1ma - - 0.4 v vcc=2.5v 0.5ma - - 0.4 vcc=2.0v 0.33ma - - 0.4 output high voltage v oh i oh vcc=3.0v -1.0ma 2.4 - - v vcc=2.5v -0.5ma 2.0 - - vcc=2.0v -0.44ma 1.6 - - standby current(ttl) i sb cs 1 =v ih, or cs 2 =v il - - 0.3 ma standby current (cmos) KM68FS1000Z km68fr1000z i sb1 cs 1 3 vcc-0.2v cs 2 3 vcc-0.2v or cs 2 0.2v, other input =0~vcc low low power - 0.05 5 2) m a KM68FS1000Zi km68fr1000zi low low power - 0.05 5 2) m a
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary test conditions (1.test load and test input/output reference)* * see test condition of dc and operating characteristics item value remark input pulse level 0.4 to 2.2v v cc =3.0v, 2.5v 0.4 to 1.8v v cc =2.0v input rising and falling time 5ns - input and output reference voltage 1.5v v cc =3.0v 1.1v v cc =2.5v 0.9v v cc =2.0v, output load (see right) c l =100pf see test condition #2 c l =30pf ac operating conditions c l * * including scope and jig capacitance r 2 *** r 1 ** v tm *** **r 1 =3070 w , r 2 =3150 w ***v tm =2.8v for vcc = 3.0v/3.3v test conditions (2. temperature and vcc conditions ) * all the parameters are measured with 30pf test load product family temperature vcc range typical supply v cc speed comments km68fr1000z 0~70 c 1.8(min)~2.7(max) 2.0v 0.2 operation 300*ns commercial KM68FS1000Z 0~70 c 2.3(min)~3.3(max) 2.5v 0.2 operation 150*ns 3.0v 0.3 operation 100*ns km68fr1000zi -40~85 c 1.8(min)~2.7(max) 2.0v 0.2 operation 300*ns industrial KM68FS1000Zi -40~85 c 2.3(min)~3.3(max) 2.5v 0.2 operation 150*ns 3.0v 0.3 operation 100*ns 2.3v for vcc = 2.5v 1.8v for vcc = 2.0v
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary ac characteristics parameter list symbol speed bins units 100ns 150ns 300ns min max min max min max read read cycle time t rc 100 - 150 - 300 - ns address access time t aa - 100 - 150 - 300 ns chip select to output t co1 - 100 - 150 - 300 ns output enable to valid output t oe - 50 - 75 - 150 ns chip select to low-z output t lz1, t lz2 10 - 20 - 50 - ns output enable to low-z output t olz 5 - 20 - 30 - ns chip disable to high-z output t hz1, t hz2 0 30 0 40 0 60 ns output disable to high-z output t ohz 0 30 0 40 0 60 ns output hold from address change t oh 15 - 15 - 30 - ns write write cycle time t wc 100 - 150 - 300 - ns chip select to end of write t cw 80 - 120 - 300 - ns address set-up time t as 0 - 0 - 0 - ns address valid to end of write t aw 80 - 120 - 300 - ns write pulse width t wp 70 - 100 - 200 - ns write recovery t wr 0 - 0 - 0 - ns write to output high-z t whz 0 30 0 40 0 60 ns data to write time overlap t dw 40 - 60 - 120 - ns data hold from write time t dh 0 - 0 - 0 - ns end write to output low-z t ow 5 - 5 - 20 - ns
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary data retention characteristics * 1) commercial product : t a =0 to 70 c, unless otherwise specified 2) industrial product : t a =-40 to 85 c, unless otherwise specified ** t a =25 c, the value is too small to detect by test machine, 0.01 m a statistically *** cs 1 3 vcc-2.0v, cs 2 3 vcc-2.0v( cs 1 controlled) or cs 2 2.0v(cs 2 controlled) item symbol test condition* min typ** max unit vcc for data retention v dr cs 1 *** 3 vcc-0.2v 1.5 - 3.6 v data retention current i dr vcc=3.0v cs 1 3 vcc-0.2v low low power - 0.05 5 m a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - - data retention timing diagram v cc 3.3/3.0/2.7/2.3/1.8v v ih v dr cs gnd data retention mode cs 3 v cc - 0.2v 1) cs 1 controlled t sdr t rdr v cc 2.3v cs 2 v dr 0.4v gnd data retention mode cs 2 0.2v 2) cs 2 controlled 2.0v t sdr t rdr
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary address data out previous data valid data valid timming diagrams timing waveform of read cycle(2) ( we =v ih ) notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. timing waveform of read cycle (1) (address controlled) ( cs = oe =v il , we =v ih, ub or, and lb =v il ) t aa t oh t rc data valid high-z cs 1 address oe data ou t cs 2 t oh t aa t olz t lz t ohz t hz(1,2) t co1 t rc t co2 t oe
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary timing waveform of write cycle(1) ( we controlled) address cs 1 timing waveform of write cycle(2) ( cs 1 controlled) address cs 1 cs 2 data undefined data valid we data in data out data valid we data in high-z high-z data valid data out high-z high-z cs 2 t wc t cw(2) t wr2(4) t aw t cw(2) t wp(1) t as t dw t dh t ow t whz t cw(2) t wr(4) t aw t wp(1) t dw t dh t as t wc
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary timing waveform of write cycle(3) (cs 2 controlled) notes (write cycle) 1. a write occurs during the overlap of a low cs 1 and a high cs 2 low we . a write begins at the latest transition among cs 1 going low cs 2 going high and we goes low. a write ends at the earliest transition among cs 1 going high ,cs 2 going low and we going high twp is measured from the beginning of write to the end write. 2. t cw is measured from the later of cs 1 going low or cs 2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end or write to the address change. t wr1 applied in case a write ends at cs 1 or we going high, t wr2 applied in case a write ends at cs 2 going to low. functional description * x means do care (high or low) cs 1 cs 2 we oe mode i/o 1 ~ 8 current mode h x* x x power down high-z i sb x l x x power down high-z i sb ,i sb1 l h h h output disable high-z icc l h h l read dout icc l h l x write din icc address cs 1 cs 2 data valid we data in high-z high-z data valid data out high-z high-z t wc t cw(2) t wr1(4) t aw t wp(1) t dw t dh t as(3) t cw(2)
revision 1.0 cmos sram april 1997 KM68FS1000Z, km68fr1000z family preliminary package dimensions (units : mm) m i n t y p m a x a - 0 . 7 5 - b 5 . 9 0 6 . 0 0 6 . 1 0 b 1 - 3 . 7 5 - c 7 . 9 0 8 . 0 0 8 . 1 0 c 1 - 5 . 2 5 - d 0 . 3 0 0 . 3 5 0 . 4 0 e - 0 . 8 0 0 . 8 1 e 1 - 0 . 5 5 - e 2 - 0 . 2 5 - y - - 0 . 0 8 6 5 4 3 2 1 a b c d e f g h c/2 b / 2 c b b 1 c1 b a l l # a 1 d e 2 e 1 e c d e t a i l a b b / 2 e l a s t o m e r s r a m d i e c b a l l # a 1 c/2 b o t t o m v i e w s i d e v i e w t o p v i e w 0.55/typ. 0.32/typ. 0.32/typ. a y e l a s t o m e r 0 . 4 2 / t y p . d i e d e t a i l a n o t e s . 1 . b u m p c o u n t s : 4 8 ( 8 r o w x 6 r o w ) 2 . b u m p p i t c h : ( x , y ) = ( 0 . 7 5 x 0 . 7 5 ) ( t y p . ) 3 . a l l t o l e r e n c e a r e + / - 0 . 0 5 0 u n l e s s o t h e r w i s e s p e c i f i e d . 4 . t y p : t y p i c a l 5 . y i s c o p l a n a r i t y : 0 . 0 8 ( m a x )

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